1. Field Of The Invention
The present invention relates to circuits which employ JTAG boundary-scan architecture, and, in particular, to circuits having bus output enables controllable via a JTAG test register.
2. Description Of The Related Art
A well known method for testing complex integrated circuitry on, for example, a printed circuit card, is the IEEE 1149.1 boundary-scanned standard originated by the International Joint Test Action Group (JTAG), hereby incorporated by reference. One implementation of this standard involves designing components (e.g., integrated circuits) for serial boundary-scanned testing by providing shift-register elements daisy chained to form a path around the periphery of an integrated circuit component.
The general concept for serial testing using JTAG is to shift serial data into and through a number of integrated circuit components, stimulating the circuitry therein or to generate predefined output signals from the circuitry. Thereafter, data generated by the integrated circuit components or received on inputs of the integrated circuit components are shifted from the integrated circuit components to a JTAG master testing circuit.
If the data stream returned to the master testing circuit is not as expected, then a malfunction in the circuit is detected by the testing circuit. A careful analysis under software control of the deviations in the data stream may isolate any malfunctions within a circuit.
In certain instances, it is desirable to isolate a single chip, or one or more bus connections of a chip on a PC card from the rest of the circuitry on the PC card. For example, an integrated circuit (IC) chip may include internal memory bus interface circuitry, PCI bus interface circuitry, microprocessor (.mu.P) bus interface circuitry, etc., which provide connections between the circuitry within the IC chip and the various communication buses on the PC cards. The JTAG test circuitry within the IC chip typically includes a JTAG boundary-scan data shift-register (BSR) including a bit location corresponding to each of the I/O bus connections on the IC chip. In addition, one or more bus output enable bit locations are included within the BSR. Each bus output enable bit location within the BSR chain enables the output for all or part of a bus connected to the IC chip (e.g., the processor bus, the PCI bus, the memory bus, etc.). Thus, for example, a bus output enable bit location will be associated with the PCI bus's address-data bus; another bus output enable bit will be associated with the PCI bus's control bus; etc. When the respective output enable bit location is set to the appropriate value, the output of the entire PCI bus's address-data bus interface circuitry (or the PCI bus's control interface circuitry, etc.) is enabled from the IC chip. Likewise, if the output enable bit location within the BSR is set to a non-enabling value, the entire PCI bus's address-data bus interface will assume a high impedance mode so that signals may not be transferred out of the IC chip via the PCI address-data bus interface. Of course, it will be understood to those of skill in the art, that multiple output enable bit locations of the BSR may be used to control parts of a bus interface so that, for example, 16 bits of the PCI address-data bus may be under the control of one output enable, another 16 bits under the control of another output enable, etc. Likewise, a single output enable bit in the BSR can be used to control the entire PCI bus.
If an IC chip is to be isolated from one or more of the buses connected to the IC chip, then a conventional JTAG test circuit would involve loading a data bit for each bit location within the JTAG boundary scan data register throughout the entire IC chip. Thus, for example, if four separate 64-bit buses connect to the IC chip, and each bus has a single associated bus output enable bit location in the chip's BSR, then a total of 260 BSR test bits (4.times.64+4) will be loaded into the BSR before each of the bus output enable bit locations are set. In a worst case scenario, all four of the buses are to be disabled so that the remaining 256 locations within the JTAG data register are "don't care" values. Thus, a conventional system may involve a great deal of inefficiency since because data bits must be shifted into the BSR in addition to the four output enable BSR bit locations. This situation is compounded by the fact that this chip's BSR might be in series with other chip's BSR's on the PC card or cards.
An alternative method of isolating an IC device from the other circuits on a PC card involves setting the entire chip into a high impedance mode using the "HIGHZ" instruction loaded into the JTAG instruction register. Although such a method alleviates the aforementioned problem of inefficiently disabling the buses, this solution allows for disabling either all or none of the buses.
However, certain applications require that selected buses of an IC device be enabled while others are disabled. For example, because many IC devices employ CMOS technology, it is important that at least one circuit on a given bus be enabled to drive the bus because CMOS circuits typically float when placed in a high impedance mode. Therefore, if all of the CMOS circuits on a bus are placed in a high impedance state so that no circuit is driving the bus to some definite state, then the bus will float so that it is possible that the bus will float midway between a high logic level and a low logic level. Such a floating condition is not desirable because a CMOS input which receives a floating input signal may have both input transistors in a partially on condition, connecting power to ground, and causing the CMOS transistors to overheat and possibly to be damaged. Consequently, when disabling a bus connection of an IC device connected to multiple buses, it is sometimes desirable to drive one or more of the remaining buses connected to the IC device so that those buses not currently being tested do not float. Therefore, a JTAG system which places either all or none of the bus connections on an IC device in a high impedance mode is not suitable for certain applications.